/*************************************************/
//利用状态机实现3-8译码器的输出信号,输出译码信号与真值表一致
reg [7:00]y_r;
always@(posedge clk_25m or negedge rst_n)
begin
if(!rst_n)
begin
y_r <= 8'b000000000;
end
else
begin
case(a)
3'b000:begin
y_r <= 8'b00000001;
end
3'b001:begin
y_r <= 8'b00000010;
end
3'b010:begin
y_r <= 8'b00000100;
end
3'b011:begin
y_r <= 8'b00001000;
end
3'b100:begin
y_r <= 8'b00010000;
end
3'b101:begin
y_r <= 8'b00100000;
end
3'b110:begin
y_r <= 8'b01000000;
end
3'b111:begin
y_r <= 8'b10000000;
end
default:begin
y_r <= 8'b000000000;
end
endcase
end
end
assign y = y_r;